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71M6533/G/H and 71M6534/H Data Sheet
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter.
FDS_6533_6534_004
FIR_LEN[1:0]
2007[3:2]
1
1
R/W
[ M40MHZ, M26MHZ ]
[00], [10], or [11]
[01]
FIR_LEN [1:0]
00
01
10
00
Resulting FIR
Filter Cycles
138
288
384
186
Resulting
ADC Gain
0.110017
1.000
2.37037
0.113644
01
10
384
588
1.000
3.590363
FL_BANK[1:0]
FL_BANK[2:0] ?
FLSH_ERASE
[7:0]
SFR B6[1:0]
SFR B6[2:0]
SFR 94[7:0]
1
0
1
0
R/W
W
Flash bank selection. Flash memory above 32 k is mapped to the MPU address space
from 0x8000 to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in
flash is mapped to FL_BANK[1:0] or FL_BANK[2:0] (71M6534 only ) , MPU Address[14:0].
FL_BANK[] is reset by the erase cycle.
Flash Erase Initiate. (Default = 0x00) . FLSH_ERASE is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR @ SFR 0xB7.
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE will have no effect. The erase cycle is not
completed until 0x00 is written to FLSH_ERASE .
Mass Erase Enable.
FLSH_MEEN
FLSH_PGADR
[5:0]
FLSH_PWE
FOVRIDE
SFR B2[1]
SFR B7 [7:2]
SFR B2[0]
20FD[4]
0
0
0
0
0
0
0
0
W
W
R/W
R/W
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Flash Page Erase Address. (Default = 0x00)
FLSH_PGADR[5:0] with FL_BANK[2:0] , sets the Flash Page Address (page 0 through
127) that will be erased during the Page Erase cycle.
Must be re-written for each new Page Erase cycle.
Program Write Enable. This bit must be cleared by the MPU after each byte write
operation. Writes to this bit are inhibited when interrupts are enabled.
0 = MOVX commands refer to XRAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
Permits the values written by the MPU to temporarily override the values in the fuse
register (reserved for production test).
86
Rev 2
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